ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the 1st conference on Computing frontiers
Layer Assignment echniques for Low Energy in Multi-Layered Memory Organisations
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
DRDU: A data reuse analysis technique for efficient scratch-pad memory management
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Incremental hierarchical memory size estimation for steering of loop transformations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
EURASIP Journal on Applied Signal Processing
Real-time video convolutional face finder on embedded platforms
EURASIP Journal on Embedded Systems
Journal of Signal Processing Systems
Proceedings of the 17th international conference on Parallel architectures and compilation techniques
Trade-offs in loop transformations
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Journal of Signal Processing Systems
Multiprocessor, Multithreading and Memory Optimization for On-Chip Multimedia Applications
Journal of Signal Processing Systems
ACM Transactions on Embedded Computing Systems (TECS)
Compiler-directed scratch pad memory optimization for embedded multiprocessors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
Combined loop transformation and hierarchy allocation for data reuse optimization
Proceedings of the International Conference on Computer-Aided Design
Memory hierarchy energy cost of a direct filtering implementation of the wavelet transform
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Optimizing memory hierarchy allocation with loop transformations for high-level synthesis
Proceedings of the 49th Annual Design Automation Conference
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Efficient exploration of temporal locality in the memory accesses on array signals can have a very large impact on the power consumption in embedded data dominated applications.The effective use of an optimized custom memory hierarchy or a customized software controlled mapping on a predefined hierarchy, is crucial for this.One recently effective systematic techniques to deal with this specific design step have begun to appear.They were still limited in their exploration scope.In this paper we introduce an extended formalized methodology based on an analytical model of the data reuse of a signal.The cost parameters derived from this model define the search space to explore and allow us to exploit the maximum data reuse possible.The result is an auomated design technique to find power efficient memory hierarchies and generate the corresponding optimized code.