A data locality optimizing algorithm
PLDI '91 Proceedings of the ACM SIGPLAN 1991 conference on Programming language design and implementation
Scalar replacement in the presence of conditional control flow
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PLDI '95 Proceedings of the ACM SIGPLAN 1995 conference on Programming language design and implementation
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IEEE Transactions on Computers
Loop fusion for memory space optimization
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International Journal of Parallel Programming
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Optimizing inter-nest data locality
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Performance Analysis of Four Memory Consistency Models for Multithreaded Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
ESOP '02 Proceedings of the 11th European Symposium on Programming Languages and Systems
Tiling and Memory Reuse for Sequences of Nested Loops
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
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PACT '99 Proceedings of the 1999 International Conference on Parallel Architectures and Compilation Techniques
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Proceedings of the conference on Design, automation and test in Europe
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Proceedings of the 41st annual Design Automation Conference
Optimizing the memory bandwidth with loop fusion
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Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design
Proceedings of the 42nd annual Design Automation Conference
Locality-conscious workload assignment for array-based computations in MPSOC architectures
Proceedings of the 42nd annual Design Automation Conference
Application-Level Memory Optimization for MPSoC
RSP '06 Proceedings of the Seventeenth IEEE International Workshop on Rapid System Prototyping
System-on-Chip: Next Generation Electronics (Circuits, Devices and Systems) (Circuits, Devices and Systems)
DRDU: A data reuse analysis technique for efficient scratch-pad memory management
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MPSoC memory optimization using program transformation
ACM Transactions on Design Automation of Electronic Systems (TODAES)
MPSoC memory optimization for digital camera applications
DSD '07 Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools
Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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ARCS'06 Proceedings of the 19th international conference on Architecture of Computing Systems
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Multiprocessor System-on-Chip is one of the main drivers of the semiconductor industry revolution by enabling the integration of complex functionality on a single chip. The techniques for processor design and application optimizations can be combined together for more efficient design of these systems. Thus, the memory optimization techniques improving the data locality can be combined with multithreading technology, improving the overall processor efficiency. The combination of these techniques is mainly challenged by the adaptation of memory optimization techniques to the high parallelism offered by the multithreading environments. This paper presents an in-depth analysis of the impact of multiprocessor and multithreading environments on memory optimization techniques. A discussion is provided on the different types of parallelization (fine and coarse grain) and their influence on memory optimization technique. Some improvements on existing memory optimization techniques are presented as well some adaptation necessary to use them in this type of environment.