Efficient (stack) algorithms for analysis of write-back and sector memories
ACM Transactions on Computer Systems (TOCS)
A Theory for Multiresolution Signal Decomposition: The Wavelet Representation
IEEE Transactions on Pattern Analysis and Machine Intelligence
Wavelets and subband coding
Analytical energy dissipation models for low-power caches
ISLPED '97 Proceedings of the 1997 international symposium on Low power electronics and design
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Energy-driven integrated hardware-software optimizations using SimplePower
Proceedings of the 27th annual international symposium on Computer architecture
Cache conscious data layout organization for embedded multimedia applications
Proceedings of the conference on Design, automation and test in Europe
Subband Image Coding
Global interconnect trade-off for technology over memory modules to application level: case study
Proceedings of the 2003 international workshop on System-level interconnect prediction
Reuse Distance-Based Cache Hint Selection
Euro-Par '02 Proceedings of the 8th International Euro-Par Conference on Parallel Processing
Vectorization of the 2D Wavelet Lifting Transform Using SIMD Extensions
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
Assigning Program and Data Objects to Scratchpad for Energy Reduction
Proceedings of the conference on Design, automation and test in Europe
Data Reuse Exploration Techniques for Loop-Dominated Applications
Proceedings of the conference on Design, automation and test in Europe
Aspects of cache memory and instruction buffer performance
Aspects of cache memory and instruction buffer performance
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Reducing 3D Fast Wavelet Transform Execution Time Using Blocking and the Streaming SIMD Extensions
Journal of VLSI Signal Processing Systems
Global memory optimisation for embedded systems allowed by code duplication
SCOPES '05 Proceedings of the 2005 workshop on Software and compilers for embedded systems
Line-based, reduced memory, wavelet image compression
IEEE Transactions on Image Processing
Optimal memory organization for scalable texture codecs in MPEG-4
IEEE Transactions on Circuits and Systems for Video Technology
Scalable wavelet coding for synthetic/natural hybrid images
IEEE Transactions on Circuits and Systems for Video Technology
A resolution and frame-rate scalable subband/wavelet video coder
IEEE Transactions on Circuits and Systems for Video Technology
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In the context of future dynamic applications, systems will exhibit unpredictably varying platform resource requirements. To deal with this, they will not only need to be programmable in terms of instruction set processors, but also at least partial reconfigurability will be required. In this context, it is important for applications to optimally exploit the memory hierarchy under varying memory availability. This article presents a mapping strategy for wavelet-based applications: depending on the encountered conditions, it switches to different memory optimized instantations or localizations, permitting up to 51% energy gains in memory accesses. Systematic and parameterized mapping guidelines indicate which localization should be selected when, for varying algorithmic wavelet parameters. The results have been formalized and generalized to be applicable to more general wavelet-based applications.