Design of a low power video decompression chip set for portable applications
Journal of VLSI Signal Processing Systems - Special issue on technologies for wireless computing
Global multimedia system design exploration using accurate memory organization feedback
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Custom Memory Management Methodology: Exploration of Memory Organisation for Embedded Multimedia System Design
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Memory Issues in Embedded Systems-on-Chip: Optimizations and Exploration
Low-voltage memories for power-aware systems
Proceedings of the 2002 international symposium on Low power electronics and design
Timing Models for MOS Circuits
Timing Models for MOS Circuits
How Can System-Level Design Solve the Interconnect Technology Scaling Problem?
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Proceedings of the 1st conference on Computing frontiers
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Energy-efficient dynamic memory allocators at the middleware level of embedded systems
EMSOFT '06 Proceedings of the 6th ACM & IEEE International conference on Embedded software
Journal of Systems Architecture: the EUROMICRO Journal
Proceedings of the conference on Design, automation and test in Europe
Journal of Signal Processing Systems
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In this paper we show how to exploit energy-delay trade-offs that exist due to the variation of the technology parameters for the implementation of interconnect wires. We also evaluate how these trade-offs can be propagated to the memory module level, so we can minimise the power consumption of the entire memory organisation (i.e., memories and connections between them). Our approach is that at future technology nodes the delay problem can be handled at the application level, so given any delay slack obtained at that level, we can exploit it to make the switching on the interconnect wires slower and thus less energy consuming. In this way, we have shown that for real-life applications the power consumption at future technology nodes can be reduced by about 34%, when compared to the option provided by the ITRS roadmap. This is achieved by, instead of using the very fast and power hungry wires, selectively using slower and thinner interconnect wires while still meeting the application real-time constraints.