Getting to the bottom of deep submicron II: a global wiring paradigm
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Low power design challenges for the decade (invited talk)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Power-Driven Challenges in Nanometer Design
IEEE Design & Test
Repeater and current-sensing hybrid circuits for on-chip interconnects
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Current Sensing Techniques for Global Interconnects in Very Deep Submicron(VDSM) CMOS
WVLSI '01 Proceedings of the IEEE Computer Society Workshop on VLSI 2001
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Interconnects are an increasing concern in recent years, resulting in novel techniques such as current sensing. However these techniques must be designed to tradeoff delay and both dynamic and static power consumption. This paper presents an innovative approach to reduce static power in differential current-sensed interconnects. This system uses a self-timed shut-off system to reduce static currents used to bias the current sense amplifier. Results indicated that the self timed shut-off system reduced static power by 23.4% for a 10mm line in 250nm technology with no overhead in performance. On an average it reduced static power by 9.7% for 4mm-9mm lines over 180nm, 130nm, 100nm and 65nm technologies and 6% from 10mm-15mm line over the same set of technologies as before. Physical design of the system was implemented in 250nm technology along with the implementation of a test circuit, ready to be fabricated. Extensions of this shut-off mechanism may be useful for mitigating leakage power in a variety of interconnect circuits.