On the Design of a Photonic Network-on-Chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors
IEEE Transactions on Computers
Phastlane: a rapid transit optical routing network
Proceedings of the 36th annual international symposium on Computer architecture
A power-efficient all-optical on-chip interconnect using wavelength-based oblivious routing
Proceedings of the fifteenth edition of ASPLOS on Architectural support for programming languages and operating systems
Re-architecting DRAM memory systems with monolithically integrated silicon photonics
Proceedings of the 37th annual international symposium on Computer architecture
A low-power fat tree-based optical network-on-chip for multiprocessor system-on-chip
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
An Optical Wavelength Switching Architecture for a High-Performance Low-Power Photonic NoC
WAINA '11 Proceedings of the 2011 IEEE Workshops of International Conference on Advanced Information Networking and Applications
All-optical wavelength-routed noc based on a novel hierarchical topology
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Multi-Optical Network-on-Chip for Large Scale MPSoC
IEEE Embedded Systems Letters
NOCS '12 Proceedings of the 2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip
PROTON: an automatic place-and-route tool for optical networks-on-chip
Proceedings of the International Conference on Computer-Aided Design
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There is still a significant gap between the optical network-on-chip (NoC) concept and a mature interconnect technology with practical relevance. Current research aims at bridging this gap by evolving basic optical components and by developing ad-hoc design tools to enable their use for system-level design. This paper points out another cause for the design predictability gap of optical NoC topologies, namely the physical placement of network interfaces in the target floorplan. Building on this awareness, the paper compares power efficiency of the most relevant topologies proposed so far for wavelength-routed optical NoCs in the context of a 3D-stacked multi-core processor.