Stream arbitration: Towards efficient bandwidth utilization for emerging on-chip interconnects

Authors:
Chunhua Xiao;M-C. Frank Chang;Jason Cong;Michael Gill;Zhangqin Huang;Chunyue Liu;Glenn Reinman;Hao Wu
Affiliations:
Beijing University of Technology, Beijing, P. R. China;University of California, Los Angels, CA;University of California, Los Angels, CA;University of California, Los Angels, CA;Beijing University of Technology, Beijing, P. R. China;University of California, Los Angels, CA;University of California, Los Angels, CA;University of California, Los Angels, CA
Venue:
ACM Transactions on Architecture and Code Optimization (TACO) - Special Issue on High-Performance Embedded Architectures and Compilers
Year:
2013

Citing 25
Cited 0

A General Theory for Deadlock-Free Adaptive Routing Using a Mixed Set of Resources

IEEE Transactions on Parallel and Distributed Systems
Simics: A Full System Simulation Platform

Computer
Managing Wire Delay in Large Chip-Multiprocessor Caches

Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture
Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling

Proceedings of the 32nd annual international symposium on Computer Architecture
Spatial division multiplexing: a novel approach for guaranteed throughput on NoCs

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Æthereal Network on Chip: Concepts, Architectures, and Implementations

IEEE Design & Test
Performance implications of single thread migration on a chip multi-core

ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset

ACM SIGARCH Computer Architecture News - Special issue: dasCMP'05
Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Managing Distributed, Shared L2 Caches through OS-Level Page Allocation

Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
Circuit-Switched Coherence

IEEE Computer Architecture Letters
On-Chip Interconnection Architecture of the Tile Processor

IEEE Micro
RF interconnects for communications on-chip

Proceedings of the 2008 international symposium on Physical design
Corona: System Implications of Emerging Nanophotonic Technology

ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Power reduction of CMP communication networks via RF-interconnects

Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
Reactive NUCA: near-optimal block placement and replication in distributed caches

Proceedings of the 36th annual international symposium on Computer architecture
Light speed arbitration and flow control for nanophotonic interconnects

Proceedings of the 42nd Annual IEEE/ACM International Symposium on Microarchitecture
ACES: application-specific cycle elimination and splitting for deadlock-free routing on irregular network-on-chip

Proceedings of the 47th Design Automation Conference
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration

Proceedings of the Conference on Design, Automation and Test in Europe
A hybrid packet-circuit switched on-chip network based on SDM

Proceedings of the Conference on Design, Automation and Test in Europe
CloudCache: Expanding and shrinking private caches

HPCA '11 Proceedings of the 2011 IEEE 17th International Symposium on High Performance Computer Architecture
High-Level Synthesis for FPGAs: From Prototyping to Deployment

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Accelerating Sequential Applications on CMPs Using Core Spilling

IEEE Transactions on Parallel and Distributed Systems
BiN: a buffer-in-NUCA scheme for accelerator-rich CMPs

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
CHARM: a composable heterogeneous accelerator-rich microprocessor

Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Alternative interconnects are attractive for scaling on-chip communication bandwidth in a power-efficient manner. However, efficient utilization of the bandwidth provided by these emerging interconnects still remains an open problem due to the spatial and temporal communication heterogeneity. In this article, a Stream Arbitration scheme is proposed, where at runtime any source can compete for any communication channel of the interconnect to talk to any destination. We apply stream arbitration to radio frequency interconnect (RF-I). Experimental results show that compared to the representative token arbitration scheme, stream arbitration can provide an average 20% performance improvement and 12% power reduction.