A graph-oriented mapping strategy for a hypercube
C3P Proceedings of the third conference on Hypercube concurrent computers and applications: Architecture, software, computer systems, and general issues - Volume 1
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
A Delay Model for Router Microarchitectures
IEEE Micro
IEEE Transactions on Parallel and Distributed Systems
Low-Latency Virtual-Channel Routers for On-Chip Networks
Proceedings of the 31st annual international symposium on Computer architecture
QEMU: a multihost, multitarget emulator
Linux Journal
The M5 Simulator: Modeling Networked Systems
IEEE Micro
Layered switching for networks on chip
Proceedings of the 44th annual Design Automation Conference
Incremental run-time application mapping for homogeneous NoCs with multiple voltage levels
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A new approach to model virtual channels in interconnection networks
Journal of Computer and System Sciences
An investigation of credit-based flow control protocols
Proceedings of the 1st international conference on Simulation tools and techniques for communications, networks and systems & workshops
COTSon: infrastructure for full system simulation
ACM SIGOPS Operating Systems Review
Factored operating systems (fos): the case for a scalable operating system for multicores
ACM SIGOPS Operating Systems Review
The Two-Level-Turn-Model Fault-Tolerant Routing Scheme in Tori with Convex and Concave Faults
ITNG '09 Proceedings of the 2009 Sixth International Conference on Information Technology: New Generations
Scalability of network-on-chip communication architecture for 3-D meshes
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Adding mechanisms for QoS to a network-on-chip
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Queueing network models of credit-based flow control
Computers & Mathematics with Applications
Balanced Dimension-Order Routing for k-ary n-cubes
ICPPW '09 Proceedings of the 2009 International Conference on Parallel Processing Workshops
Corey: an operating system for many cores
OSDI'08 Proceedings of the 8th USENIX conference on Operating systems design and implementation
PhoenixSim: a simulator for physical-layer analysis of chip-scale photonic interconnection networks
Proceedings of the Conference on Design, Automation and Test in Europe
C?aSH: Structural Descriptions of Synchronous Hardware Using Haskell
DSD '10 Proceedings of the 2010 13th Euromicro Conference on Digital System Design: Architectures, Methods and Tools
An analysis of Linux scalability to many cores
OSDI'10 Proceedings of the 9th USENIX conference on Operating systems design and implementation
Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
In this paper we present MCoreSim, an open-source simulation framework for massively parallel and many-core computing systems based on OMNeT++. The simulator supports tile-based architectures with distributed memory and mesh-based interconnects. Its primary purpose is to allow for investigations on the impact of the heterogeneous in-chip communication latencies, as arising due to the network-on-a-chip structure of future and emerging many-core processors, on the performance of the hosted applications. We plan to use MCoreSim to study the variety of possible choices in realizing a suitable software stack for these systems, especially in terms of the choices at the kernel design level.