Scalability of network-on-chip communication architecture for 3-D meshes

Authors:
Awet Yemane Weldezion;Matt Grange;Dinesh Pamunuwa;Zhonghai Lu;Axel Jantsch;Roshan Weerasekera;Hannu Tenhunen
Affiliations:
School of Information and Communication Technologies, Department of Electronics, Computer, and Software Systems, KTH Royal Institute of Technology, Electrum 229, Kista SE 16440, Sw;Centre for Microsystems Engineering, Department of Engineering, Lancaster University, LA1 4YW, UK;Centre for Microsystems Engineering, Department of Engineering, Lancaster University, LA1 4YW, UK;School of Information and Communication Technologies, Department of Electronics, Computer, and Software Systems, KTH Royal Institute of Technology, Electrum 229, Kista SE 16440, Sw;School of Information and Communication Technologies, Department of Electronics, Computer, and Software Systems, KTH Royal Institute of Technology, Electrum 229, Kista SE 16440, Sw;Centre for Microsystems Engineering, Department of Engineering, Lancaster University, LA1 4YW, UK;Centre for Microsystems Engineering, Department of Engineering, Lancaster University, LA1 4YW, UK
Venue:
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Year:
2009

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Abstract

Design Constraints imposed by global interconnect delays as well as limitations in integration of disparate technologies make 3-D chip stacks an enticing technology solution for massively integrated electronic systems. The scarcity of vertical interconnects however imposes special constraints on the design of the communication architecture. This article examines the performance and scalability of different communication topologies for 3-D Network-on-Chips (NoC) using Through-Silicon-Vias (TSV) for inter-die connectivity. Cycle accurate RTL-level simulations are conducted for two communication schemes based on a 7-port switch and a centrally arbitrated vertical bus using different traffic patterns. The scalability of the 3-D NoC is examined under both communication architectures and compared to 2-D NoC structures in terms of throughput and latency in order to quantify the variation of network performance with the number of nodes and derive key design guidelines.