Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks

Authors:
Matt Grange;Roshan Weerasekera;Dinesh Pamunuwa;Axel Jantsch;Awet Yemane Weldezion
Affiliations:
Lancaster University, Lancaster, United Kingdom;Lancaster University, Lancaster, United Kingdom;Lancaster University, Lancaster, United Kingdom;KTH Royal Institute of Technology, Kista, Sweden;KTH Royal Institute of Technology, Kista, Sweden
Venue:
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Year:
2011

Citing 12
Cited 0

Performance Analysis of k-ary n-cube Interconnection Networks

IEEE Transactions on Computers
An efficient processor partitioning and thread mapping strategy for mesh-connected multiprocessor systems

SAC '97 Proceedings of the 1997 ACM symposium on Applied computing
Limits on Interconnection Network Performance

IEEE Transactions on Parallel and Distributed Systems
Principles and Practices of Interconnection Networks

Principles and Practices of Interconnection Networks
High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCs

VLSID '08 Proceedings of the 21st International Conference on VLSI Design
A Markovian Performance Model for Networks-on-Chip

PDP '08 Proceedings of the 16th Euromicro Conference on Parallel, Distributed and Network-Based Processing (PDP 2008)
Scalability of network-on-chip communication architecture for 3-D meshes

NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Analysis of worst-case delay bounds for on-chip packet-switching networks

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical method for evaluating network-on-chip performance

Proceedings of the Conference on Design, Automation and Test in Europe
Flow regulation for on-chip communication

Proceedings of the Conference on Design, Automation and Test in Europe
Buffer optimization in network-on-chip through flow regulation

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical approach for network-on-chip performance analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

A general expression for the average distance for meshes of any dimension and radix, including unequal radices in different dimensions, valid for any traffic pattern under zero-load condition is formulated rigorously to allow its calculation without network-level simulations. The average distance expression is solved analytically for uniform random traffic and for a set of local random traffic patterns. Hot spot traffic patterns are also considered and the formula is empirically validated by cycle true simulations for uniform random, local, and hot spot traffic. Moreover, a methodology to attain closed-form solutions for other traffic patterns is detailed. Furthermore, the model is applied to guide design decisions. Specifically, we show that the model can predict the optimal 3-D topology for uniform and local traffic patterns. It can also predict the optimal placement of hot spots in the network. The fidelity of the approach in suggesting the correct design choices even for loaded and congested networks is surprising. For those cases we studied empirically it is 100%.