A high abstraction, high accuracy power estimation model for networks-on-chip
Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
Workload characterization and its impact on multicore platform design
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling
Microelectronics Journal
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
A signature-based power model for MPSoC on FPGA
VLSI Design
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Traffic models exert different message flows in a network and have a considerable effect on power consumption through different applications. So a good power analysis should consider traffic models. In this paper we present power and throughput models in terms of traffic rate parameters for the most popular traffic models, i.e. Uniform, Local, HotSpot and First Matrix Transpose (FMT) as a permutational traffic model. We also select Mesh topology as the most prominent NoC topology and validate the presented models by comparing our results against simulation results from Synopsys Power Compiler and Modelsim. From the comparison, we show that our modeling approach leads to average error of 2% for power and 2.8% for throughput modeling.