Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations
SBCCI '03 Proceedings of the 16th symposium on Integrated circuits and systems design
A Systematic Approach to Exploring Embedded System Architectures at Multiple Abstraction Levels
IEEE Transactions on Computers
PowerViP: Soc power estimation framework at transaction level
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Energy-aware mapping for tile-based NoC architectures under performance constraints
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
High-level power analysis for multi-core chips
CASES '06 Proceedings of the 2006 international conference on Compilers, architecture and synthesis for embedded systems
Power macromodeling of MPSoC message passing primitives
ACM Transactions on Embedded Computing Systems (TECS) - Special Section LCTES'05
Rapid energy estimation for hardware-software codesign using FPGAs
EURASIP Journal on Embedded Systems
A framework for rapid system-level exploration, synthesis, and programming of multimedia MP-SoCs
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A framework for system-level modeling and simulation of embedded systems architectures
EURASIP Journal on Embedded Systems
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
Proceedings of the 40th Annual IEEE/ACM International Symposium on Microarchitecture
VLSID '08 Proceedings of the 21st International Conference on VLSI Design
Accurate and fast system-level power modeling: An XScale-based case study
ACM Transactions on Embedded Computing Systems (TECS)
Daedalus: toward composable multimedia MP-SoC design
Proceedings of the 45th annual Design Automation Conference
A Modular Approach to Model Heterogeneous MPSoC at Cycle Level
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
System-Level Performance Estimation for Application-Specific MPSoC Interconnect Synthesis
SASP '08 Proceedings of the 2008 Symposium on Application Specific Processors
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
Exploring NoC-Based MPSoC Design Space with Power Estimation Models
IEEE Design & Test
A High-Level Power Model for MPSoC on FPGA
IPDPSW '11 Proceedings of the 2011 IEEE International Symposium on Parallel and Distributed Processing Workshops and PhD Forum
Hybrid system level power consumption estimation for FPGA-based MPSoC
ICCD '11 Proceedings of the 2011 IEEE 29th International Conference on Computer Design
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This paper presents a framework for high-level power estimation of multiprocessor systems-on-chip (MPSoC) architectures on FPGA. The technique is based on abstract execution profiles, called event signatures, and it operates at a higher level of abstraction than, for example, commonly used instruction-set simulator (ISS)-based power estimation methods and should thus be capable of achieving good evaluation performance. As a consequence, the technique can be very useful in the context of early system-level design space exploration. We integrated the power estimation technique in a system-level MPSoC synthesis framework. Subsequently, using this framework, we designed a range of different candidate architectures which contain different numbers of MicroBlaze processors and compared our power estimation results to those from real measurements on a Virtex-6 FPGA board.