A signature-based power model for MPSoC on FPGA
VLSI Design
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This paper proposes a system-level cycle-based framework to model and design heterogeneous Multiprocessor Systemson-Chip (MPSoC), called GRAPES. The approach features flexibility and modularity maintaining high simulation speed despite modeling at cycle level. Intellectual Property (IP) system modules can be described as C++or System C entities and they are wrapped into C++ objects, called plug-ins. Plug-ins, that are modeled by the Transaction Level Modeling (TLM) style, are managed by the GRAPES kernel, which is the core of the simulation framework. GRAPES structural approach permits to easily model run-time reconfiguration and power modeling. Furthermore, GRAPES has been used to model and to simulate a case study: a scalable and heterogeneous MPSoC based on Network-on-Chip (NoC)interconnect.