Exploring dynamic mapping impact on NoC-based MPSoCs performance using a model-based framework
Proceedings of the 24th symposium on Integrated circuits and systems design
A signature-based power model for MPSoC on FPGA
VLSI Design
Enabling Adaptive Techniques in Heterogeneous MPSoCs Based on Virtualization
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Efficient execution of networked MPSoC models by exploiting multiple platform levels
International Journal of Reconfigurable Computing - Special issue on Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)
Power-aware dynamic mapping heuristics for NoC-based MPSoCs using a unified model-based approach
ACM Transactions on Embedded Computing Systems (TECS)
Creation of ESL power models for communication architectures using automatic calibration
Proceedings of the 50th Annual Design Automation Conference
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This model-based methodology and supporting toolset lets designers estimate application-specific network-on-chip (NoC) power dissipation at early stages of the design flow. An actor-oriented simulation framework captures the NoC's dynamic behavior and feeds its parameters to a rate-based power estimation model. Integrating this model into the proposed design flow enables the analysis of different design parameters and the identification of the most power-efficient application platform mappings.