Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Power estimation of embedded systems: a hardware/software codesign approach
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The design and use of simplepower: a cycle-accurate energy estimation tool
Proceedings of the 37th Annual Design Automation Conference
Wattch: a framework for architectural-level power analysis and optimizations
Proceedings of the 27th annual international symposium on Computer architecture
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Exploring NoC-Based MPSoC Design Space with Power Estimation Models
IEEE Design & Test
PowerDepot: integrating IP-based power modeling with ESL power analysis for multi-core SoC designs
Proceedings of the 48th Design Automation Conference
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Power consumption is an important factor in chip design. The fundamental design decisions drawn during early design space exploration at electronic system level (ESL) have a large impact on the power consumption. This requires to estimate power already at ESL, which is usually not possible using standard ESL component libraries due to missing power models. This work proposes a methodology that allows extension of ESL models with a power model and to automatically calibrate it to match a power trace obtained by gate-level simulation or measurements. Two case studies show that the methodology is suitable even for complex communication architectures.