Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Methodology for hardware/software co-verification in C/C++ (short paper)
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
System Level Power Modeling and Simulation of High-End Industrial Network-on-Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 3
Power Monitors: A Framework for System-Level Power Estimation Using Heterogeneous Power Models
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
PowerViP: Soc power estimation framework at transaction level
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
System-level power-performance trade-offs in bus matrix communication architecture synthesis
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis
VLSID '07 Proceedings of the 20th International Conference on VLSI Design held jointly with 6th International Conference: Embedded Systems
Power estimation methodology for a high-level synthesis framework
ISQED '09 Proceedings of the 2009 10th International Symposium on Quality of Electronic Design
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
Creation of ESL power models for communication architectures using automatic calibration
Proceedings of the 50th Annual Design Automation Conference
Virtual platforms: breaking new grounds
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we introduce an integrated power methodology for multi-core SoC designs. It features not only a bottom-up IP-based power modeling for all kinds of IP components ranging from hardware accelerators, processors, and memory blocks, but also a top-down system-wide ESL power estimation formulation. By linking these two methods of different levels of abstraction, one can thereby easily profile the power consumption of a multi-core SoC running a complete application while retaining high accuracy of estimation. We have realized the proposed methodology into two software tools: (1) PowerMixerIP, an IP-based power model builder that uses different strategies to build versatile power models for general IPs and processor IPs, and (2) PowerDepot, an ESL power estimation tool that can interact with the users in a simple way and then generate the needed power monitors to be embedded into the ESL design in SystemC for super-fast power estimation so as to facilitate early-stage system-wide power profiling. The application of these tools on a dual-core real-life designs executing an H. 264 shows that the average error of the ESL power estimation is less than 2%, while the speedup can be up to 2400X when comparing to gate-level simulation.