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Parallel Computer Architecture: A Hardware/Software Approach
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A Delay Model and Speculative Architecture for Pipelined Routers
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Microarchitecture of a High-Radix Router
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Proceedings of the 20th annual international conference on Supercomputing
Leveraging Optical Technology in Future Bus-based Chip Multiprocessors
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
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On the Design of a Photonic Network-on-Chip
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IEEE Micro
A Multi-Drop Transmission-Line Interconnect in Si LSI
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0
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RF interconnects for communications on-chip
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Corona: System Implications of Emerging Nanophotonic Technology
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The PARSEC benchmark suite: characterization and architectural implications
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Phastlane: a rapid transit optical routing network
Proceedings of the 36th annual international symposium on Computer architecture
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Main-stream general-purpose microprocessors require a collection of high-performance interconnects to supply the necessary data movement. The trend of continued increase in core count has prompted designs of packet-switched network as a scalable solution for future-generation chips. However, the cost of scalability can be significant and especially hard to justify for smaller-scale chips. In contrast, a circuit-switched bus using transmission lines and corresponding circuits offers lower latencies and much lower energy costs for smaller-scale chips, making it a better choice than a full-blown network-on-chip (NoC) architecture. However, shared-medium designs are perceived as only a niche solution for small- to medium-scale chips. In this paper, we show that there are many low-cost mechanisms to enhance the effective throughput of a bus architecture. When a handful of highly cost-effective techniques are applied, the performance advantage of even the most idealistically configured NoCs becomes vanishingly small. We find transmission line-based buses to be a more compelling interconnect even for large-scale chip-multiprocessors, and thus bring into doubt the centrality of packet switching in future on-chip interconnect.