Evaluating on-die interconnects for a 4 TB/s router

Authors:
Keith D. Underwood;Eric Borch;John Sizer;Timothy Stremcha;Michael Strom
Affiliations:
Intel Federal, Knoxville, TN, USA;Intel Federal, Knoxville, TN, USA;Open-Silicon, Inc., Eau Claire, WI, USA;Open-Silicon, Inc, Eau Claire, WI, USA;Open-Silicon, Inc., Eau Claire, WI, USA
Venue:
Proceedings of the 27th international ACM conference on International conference on supercomputing
Year:
2013

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Abstract

Future high performance computing networks will exploit routers with both high port counts and high port bandwidth. Scalable on-die interconnects will be needed to insure that the router can sustain its full bandwidth for a variety of traffic patterns. Otherwise, blocking behavior within a router can be encountered by a variety of challenging HPC traffic patterns. We examine the router on-die interconnect problem in the context of a hypothetical 4 TB/s router, including throughput on various traffic patterns and die area considerations. The results indicate that the on-die topologies that have been used in the past require either too much area, or achieve too little performance. We present three topologies (two adaptations of existing topologies, and one new topology) that can deliver area-efficient sustained performance.