Communications of the ACM
Measuring parallelism in algorithms
Euromicro 91 Proceedings of the seventeenth Euromicro conference on Software and hardware : specification and design: specification and design
Parallelism measures of task graphs for multiprocessors
Microprocessing and Microprogramming
IEEE Transactions on Parallel and Distributed Systems
Benchmark Evaluation of the IBM SP2 for Parallel Signal Processing
IEEE Transactions on Parallel and Distributed Systems
Static scheduling algorithms for allocating directed task graphs to multiprocessors
ACM Computing Surveys (CSUR)
Contention-free communication scheduling for array redistribution
Parallel Computing
Hypertool: A Programming Aid for Message-Passing Systems
IEEE Transactions on Parallel and Distributed Systems
Automatic task graph generation techniques
HICSS '95 Proceedings of the 28th Hawaii International Conference on System Sciences
Communication Contention in Task Scheduling
IEEE Transactions on Parallel and Distributed Systems
Performance, Power Efficiency and Scalability of Asymmetric Cluster Chip Multiprocessors
IEEE Computer Architecture Letters
Amdahl's Law in the Multicore Era
Computer
The Future of Computer Technology and its Implications for the Computer Industry
The Computer Journal
Validity of the single processor approach to achieving large scale computing capabilities
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
Reevaluating Amdahl's law in the multicore era
Journal of Parallel and Distributed Computing
Contention-aware scheduling with task duplication
Journal of Parallel and Distributed Computing
CIT '10 Proceedings of the 2010 10th IEEE International Conference on Computer and Information Technology
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Multicore chips are emerging as the mainstream solution for high performance computing. Generally, communication overheads cause large performance degradation in multi-core collaboration. Interconnects in large scale are needed to deal with these overheads. Amdahl's and Gustafson's law have been applied to multi-core chips but inter-core communication has not been taken into account. In this paper, we introduce interconnection into Amdahl's and Gustafson's law so that these laws work more precisely in the multi-core era. We further propose an area cost model and analyse our speedup models under area constraints. We find optimized parameters according to our speedup model. These parameters provide useful feedbacks to architects at an initial phase of their designs. We also present a case study to show the necessity of incorporating interconnection into Amdahl's and Gustafson's law.