Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Proceedings of the 7th ACM international conference on Computing frontiers
Efficient OpenMP data mapping for multicore platforms with vertically stacked memory
Proceedings of the Conference on Design, Automation and Test in Europe
Design space exploration of a mesochronous link for cost-effective and flexible GALS NOCs
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Conference on Design, Automation and Test in Europe
Mesochronous NoC technology for power-efficient GALS MPSoCs
Proceedings of the Fifth International Workshop on Interconnection Network Architecture: On-Chip, Multi-Chip
ARCS'11 Proceedings of the 24th international conference on Architecture of computing systems
Variability-tolerant workload allocation for MPSoC energy minimization under real-time constraints
ACM Transactions on Embedded Computing Systems (TECS)
Data mining MPSoC simulation traces to identify concurrent memory access patterns
Proceedings of the Conference on Design, Automation and Test in Europe
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Modern Systems on Chip strongly rely on highly complex, specialized, mixed hardware software sub systems to handle processing intensive tasks: 3D graphic, imaging, video, software radio, positioning... Cost and difficulty of super integration, lack of flexibility, little resource sharing combined with a new class of issues attached to deep submicron process variability, reliability, open opportunities to revisit more regular, programmable approaches as an alternative. Will our industry see the emergence of a new generation of standard mega cells that can be assembled as homogeneous many cores fabrics as an alternative to today's heterogeneous SoCs? We strongly believe that the answer is yes and in this talk we will go through the many folds of this question.