Reducing memory latency via non-blocking and prefetching caches
ASPLOS V Proceedings of the fifth international conference on Architectural support for programming languages and operating systems
A distributed development environment for embedded software
Software—Practice & Experience
Fast Algorithms for Mining Association Rules in Large Databases
VLDB '94 Proceedings of the 20th International Conference on Very Large Data Bases
gprof: a call graph execution profiler
ACM SIGPLAN Notices - Best of PLDI 1979-1999
Frequent pattern mining for kernel trace data
Proceedings of the 2008 ACM symposium on Applied computing
EXDAMS: extendable debugging and monitoring system
AFIPS '69 (Spring) Proceedings of the May 14-16, 1969, spring joint computer conference
Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip
SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design
Destination-based adaptive routing on 2D mesh networks
Proceedings of the 6th ACM/IEEE Symposium on Architectures for Networking and Communications Systems
Strategic directions towards multicore application specific computing
Proceedings of the Conference on Design, Automation and Test in Europe
Automatic assertion extraction via sequential data mining of simulation traces
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Frequent Instruction Sequential Pattern Mining in Hardware Sample Data
ICDM '10 Proceedings of the 2010 IEEE International Conference on Data Mining
HOPE: hotspot congestion control for Clos network on chip
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Diagnosing root causes of system level performance violations
Proceedings of the International Conference on Computer-Aided Design
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Due to a growing need for flexibility, massively parallel Multiprocessor SoC (MPSoC) architectures are currently being developed. This leads to the need for parallel software, but poses the problem of the efficient deployment of the software on these architectures. To address this problem, the execution of the parallel program with software traces enabled on the platform and the visualization of these traces to detect irregular timing behavior is the rule. This is error prone as it relies on software logs and human analysis, and requires an existing platform. To overcome these issues and automate the process, we propose the conjoint use of a virtual platform logging at hardware level the memory accesses and of a data-mining approach to automatically report unexpected instructions timings, and the context of occurrence of these instructions. We demonstrate the approach on a multiprocessor platform running a video decoding application.