Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study

Authors:
H. F. Tatenguem;D. Ludovici;A. Strano;D. Bertozzi;H. Reinig
Affiliations:
University of Ferrara, Ferrara, Italy;University of Ferrara, Ferrara, Italy;University of Ferrara, Ferrara, Italy;University of Ferrara, Ferrara, Italy;Intel Mobile Communications, Munich, Germany
Venue:
Proceedings of the 4th International Workshop on Network on Chip Architectures
Year:
2011

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Abstract

Fine-grained (per-core) multi-synchronous systems calls for new clocking strategies and new architecture design techniques. This paper compares two fundamental multi-synchronous implementation variants based on the extensive use of dual-clock FIFOs vs mesochronous synchronizers respectively. The architecture-homogeneous experimental setting, the cost-effective merging of synchronizers with NoC switch buffers, the sharing of as many physical synthesis steps as possible between the two architectures and the requirements of a realistic full-HD video playback application are the key innovations of this study.