Multisynchronous and Fully Asynchronous NoCs for GALS Architectures

Authors:
Abbas Sheibanyrad;Alain Greiner;Ivan Miro-Panades
Affiliations:
TIMA Laboratory;Laboratoire d'Informatique de Paris 6;French Atomic Energy Commission, Grenoble
Venue:
IEEE Design & Test
Year:
2008

Citing 0
Cited 10

A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors

NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Hardware/software support for adaptive work-stealing in on-chip multiprocessor

Journal of Systems Architecture: the EUROMICRO Journal
Quasi delay-insensitive high speed two-phase protocol asynchronous wrapper for network on chips

Journal of Computer Science and Technology
Hermes-a - an asynchronous NoC router with distributed routing

PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Low-energy GALS NoC with FIFO-Monitoring dynamic voltage scaling

Microelectronics Journal
A low-latency adaptive asynchronous interconnection network using bi-modal router nodes

NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Contrasting multi-synchronous MPSoC design styles for fine-grained clock domain partitioning: the full-HD video playback case study

Proceedings of the 4th International Workshop on Network on Chip Architectures
Cost-efficient buffer sizing in shared-memory 3D-MPSoCs using wide I/O interfaces

Proceedings of the 49th Annual Design Automation Conference
A transition-signaling bundled data NoC switch architecture for cost-effective GALS multicore systems

Proceedings of the Conference on Design, Automation and Test in Europe
Advances in asynchronous logic: from principles to GALS & NoC, recent industry applications, and commercial CAD tools

Proceedings of the Conference on Design, Automation and Test in Europe

Quantified Score

Hi-index	0.00

Visualization

Abstract

Networks on chips constitute a new design paradigm for communication infrastructures in large multiprocessor SoCs. NoCs can use the GALS technique to address the difficulty of distributing a synchronous clock signal on the entire chip area. This article describes two approaches to implementing a distributed NoC in a GALS environment.