Computer/interactive cleanup of non-gridded PWB's after automatic routing
DAC '77 Proceedings of the 14th Design Automation Conference
Automatic PC board routing cleanup procedures
ACM SIGDA Newsletter
Graph Theory with Applications to Engineering and Computer Science (Prentice Hall Series in Automatic Computation)
Layout optimization by pattern modification
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A “non-restrictive” artwork verification program for printed circuit boards
DAC '82 Proceedings of the 19th Design Automation Conference
Hi-index | 0.00 |
Layout optimization involves interconnection wiring modifications, which improve aesthetic appearance, fabrication characteristics, routability, and reliability of routed boards/chips. Requirements and capabilities of a general purpose layout optimizer are presented, then organization and processing flow of the program are outlined. The functional decomposition and modular structure of this system are presented. Results achieved by using the verifier/optimizer on large printed circuit boards and gate arrays are given.