Tilings and patterns
VLSI array processors
Digital system design using field programmable gate arrays
Digital system design using field programmable gate arrays
Compression-relaxation: a new approach to performance driven placement for regular architectures
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
FPGAs and cellular algorithms: two implementation examples
Journal of Systems Architecture: the EUROMICRO Journal - Special quintuple issue: Euromicro 1995 short contributions
The parallel execution of DO loops
Communications of the ACM
Computer and Robot Vision
Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays
IEEE Transactions on Parallel and Distributed Systems
A reconfigurable data-localised array for morphological algorithms
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Implementing GCD Systolic Arrays on FPGA
FPL '94 Proceedings of the 4th International Workshop on Field-Programmable Logic and Applications: Field-Programmable Logic, Architectures, Synthesis and Applications
FPGA Implementation of a Rational Adder
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Compiling Regular Arrays onto FPGAs
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
A 800 Mpixel/sec reconfigurable image correlator on XC6216
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
A Timing-Constrained Incremental Routing Algorithm for Symmetrical FPGAs
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Architectural descriptions for FPGA circuits
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
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The structure of Field Programmable Gate Arrays (FPGAs) naturally fits that of fine grain array algorithms. The paper investigates the geometrical and layout-related implementation problems of FPGA-based processor arrays. A general methodology for implementing parametrized array processors on FPGAs is presented. Then, a detailed layout algorithm is proposed. A new feature of the algorithm is the uniform treatment of inter- and intra-module nets that allows the layout of the basic processor to be optimized with respect to the critical path of the whole, arbitrarily large processor array. The approach is demonstrated on a massively parallel processor array for binary morphology.