Configurable hardware: two case studies of micro-grain computation
Systolic array processors
Higher order logic and hardware verification
Higher order logic and hardware verification
From Behavior to Structure: High-Level Synthesis
IEEE Design & Test
Partial Evaluation of Hardware
Partial Evaluation - Practice and Theory, DIKU 1998 International Summer School
Compiling Hardware Descriptions with Relative Placement Information for Parametrised Libraries
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Debugging Techniques for Dynamically Reconfigurable Hardware
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
Formal Verification of Reconfigurable Cores
FCCM '99 Proceedings of the Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines
An Investigation of Reconfigurable Multipliers for Use in Adaptive Signal Processing
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Implementing fine grain processor arrays on field-programmable logic
Integrated Computer-Aided Engineering
A dynamic hardware generation mechanism based on partial evaluation
DCC'96 Proceedings of the 3rd international conference on Designing Correct Circuits
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Abstract: FPGA-based synthesis roofs require information about behaviour and architecture to make effective use of the limited number of cells typically available. A hardware description language which models layout and behaviour is used to elegantly specify circuit architecture. This source level information is used to efficiently translate circuit descriptions onto FPGA devices.