Partial evaluation and automatic program generation
Partial evaluation and automatic program generation
Programmable active memories: reconfigurable systems come of age
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A simulation tool for dynamically reconfigurable field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 1995 IEEE ASIC conference
Lava: hardware design in Haskell
ICFP '98 Proceedings of the third ACM SIGPLAN international conference on Functional programming
CAD for ULSI
WebScope: A Circuit Debug Tool
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Dynamic Specialisation of XC6200 FPGAs by Parial Evaluation
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Pebble: A Language for Parametrised and Reconfigurable Hardware Design
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
New CAD Framework Extends Simulation of Dynamically Reconfigurable Logic
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
XC6200 FastmapTM Processor Interface
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
Compilation tools for run-time reconfigurable designs
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Automating Production of Run-Time Reconfigurable Designs
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Architectural descriptions for FPGA circuits
FCCM '95 Proceedings of the IEEE Symposium on FPGA's for Custom Computing Machines
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Formally Analyzed Dynamic Synthesis of Hardware
The Journal of Supercomputing
A design flow for partially reconfigurable hardware
ACM Transactions on Embedded Computing Systems (TECS)
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Testing dynamically reconfigurable systems imposes new challenges which require special treatment. We present tools and techniques we developed for debugging a dynamically reconfigurable system that performs run-time constant propagation optimizations. An application for monitoring the effect of run-time specialization is presented and we show how we adapted standard testability techniques to evaluate the performance of specialized circuits. We also outline how HDLs that capture reconfiguration at a high level can assist with debugging.