Rectilinear shortest paths through polygonal obstacles in O(n(logn)2) time
SCG '87 Proceedings of the third annual symposium on Computational geometry
Shortest path queries in rectilinear worlds of higher dimension (extended abstract)
SCG '91 Proceedings of the seventh annual symposium on Computational geometry
A new hypergraph based rip-up and reroute strategy
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A flat, timing-driven design system for a high-performance CMOS processor chipset
Proceedings of the conference on Design, automation and test in Europe
A line-expansion algorithm for the general routing problem with a guaranteed solution
DAC '80 Proceedings of the 17th Design Automation Conference
A solution to line-routing problems on the continuous plane
DAC '69 Proceedings of the 6th annual Design Automation Conference
Standard-cell-based design methodology for high-performance support chips
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Provably good global routing by a new approximation algorithm for multicommodity flow
ISPD '00 Proceedings of the 2000 international symposium on Physical design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
A flat, timing-driven design system for a high-performance CMOS processor chipset
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 39th annual Design Automation Conference
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Track assignment: a desirable intermediate step between global routing and detailed routing
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
The IBM ASIC/SoC methodology--A recipe for first-time success
IBM Journal of Research and Development
A generalization of Dijkstra's shortest path algorithm with applications to VLSI routing
Journal of Discrete Algorithms
Algorithms and data structures for fast and good VLSI routing
Proceedings of the 49th Annual Design Automation Conference
BonnRoute: Algorithms and data structures for fast and good VLSI routing
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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Sequential routing algorithms using maze-running are very suitable for general Over-the-Cell-Routing but suffer often from the high memory or runtime requirements of the underlying path search routine. A new algorithm for this subproblem is presented that computes shortest paths in a rectangular grid with respect to euclidean distance. It achieves performance and memory requirements similar to fast line-search algorithms while still being optimal. An additional application for the computation of minimal rip-up sets will be presented. Computational results are shown for a detailed router based on these algorithms that is used for the design of high performance CMOS processors at IBM.