Chortle-crf: Fast technology mapping for lookup table-based FPGAs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cut ranking and pruning: enabling a general and efficient FPGA mapping solution
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Rectification method for lookup-table type FPGA's
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
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In this paper, we study the incremental technology mapping problem for lookup-table (LUT) based Field Programmable Gate Arrays (FPGAs) under incremental changes. Given a gate-level networks, a mapping solution associated with it, and a sequence of changes to the original network, we compute a new mapping solution by modifying the existing one. Moreover, we assume that the given mapping solution is depth-optimal and we are required to come up with a modified mapping solution that maintains the depth optimality. The objective of our incremental mapper is to maintain depth-optimality with very high efficiency while minimizes the modifications to the existing mapping solution. We revealed a set of sufficient conditions for maintaining depth optimal mapping solution after a sequence of incremental changes. Based on these results, we developed a very fast incremental technology mapping algorithm, called IncFlow, that runs up to 300 x faster than the well-known depth-optimal FlowMap algorithm [1](with an average of 14x speedup) while achieves the same depth-optimal mapping quality.