Integrating logic retiming and register placement
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Quality of EDA CAD Tools: Definitions, Metrics and Directions
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Stable Multiway Circuit Partitioning for ECO
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
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Many circuit modifications require only a slight adjustment to the IC layouts. General purpose placement algorithms cannot take advantage of these situations because they are designed to generate a complete placement from scratch. In this paper, we present two new algorithms to effect incremental changes on a gate array layout automatically. The algorithms will selectively relocate a number of logic elements to vacate an empty slot. The empty slot is then ready for an added logic element. Results obtained prove that the two algorithms are superior over simple-minded layout modification methods. The computation time is of O(n3/2) where n is the number of elements in the neighborhood of change in a layout. For conventional placement algorithms, n will include all the elements in the layout. Therefore, the incremental algorithms will be several orders of magnitude faster