Simultaneous floorplanning and buffer block planning

Authors:
Iris Hui-Ru Jiang;Yao-Wen Chang;Jing-Yang Jou;Kai-Yuan Chao
Affiliations:
VIA Technologies Inc., Taipei, Taiwan;National Taiwan University, Taipei, Taiwan;National Chiao Tung University, Hsinchu, Taiwan;Intel Corporation, Hillsboro, OR
Venue:
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Year:
2003

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Abstract

As technology advances and the number of interconnections among modules rapidly increases, timing closure and design convergence are the most important concerns. Hence, it is desirable to consider interconnect optimization as early as possible. In this paper, we first address simultaneous floorplanning and buffer block planning (i.e., integrating buffer block planning into floorplanning) for interconnect optimization. Experimental results show that our method can significantly improve the interconnect delay and reduce the number of buffers needed.