Methodology for repeater insertion management in the RTL, layout, floorplan and fullchip timing databases of the Itanium microprocessor

Future performance challenges in nanometer design

Proceedings of the 38th annual Design Automation Conference

Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design

Concurrent flip-flop and repeater insertion for high performance integrated circuits

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design

Low-power design methodology for an on-chip bus with adaptive bandwidth capability

Proceedings of the 40th annual Design Automation Conference

Current-mode signaling in deep submicrometer global interconnects

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)

Architecture-level synthesis for automatic interconnect pipelining

Proceedings of the 41st annual Design Automation Conference

Low-power on-chip communication based on transition-aware global signaling (TAGS)

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Driver pre-emphasis techniques for on-chip global buses

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design

A probabilistic analysis of pipelined global interconnect under process variations

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Simultaneous floorplanning and buffer block planning

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference

Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses

IEEE Transactions on Very Large Scale Integration (VLSI) Systems