Digital systems engineering
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Power-Driven Challenges in Nanometer Design
IEEE Design & Test
Low-power design methodology for an on-chip bus with adaptive bandwidth capability
Proceedings of the 40th annual Design Automation Conference
8Gb/s capacitive low power and high speed 4-PWAM transceiver design
Proceedings of the 20th symposium on Great lakes symposium on VLSI
Low-power, high-speed transceivers for network-on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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By using current-sensing differential buses with driver pre-emphasis techniques, power dissipation is reduced by 26.0% - 51.2% and peak current is reduced by 63.8%, compared to conventional repeater insertion techniques, for 10mm long buses in TSMC 0.25μm technology. This proposed architecture lowers the worst coupling capacitance to total capacitance ratio to 14.4%. It only requires 7.9% more bus routing area than single-ended designs for a 16-bit bus, and saves all of the repeater placement blockages. To further verify that the driver pre-emphasis techniques can also be applied to voltage-mode single-ended buses, a test chip in TSMC 0.18μm technology was fabricated and measured