Low-string on-chip signaling techniques: effectiveness and robustness
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
A robust self-calibrating transmission scheme for on-chip networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Driver pre-emphasis techniques for on-chip global buses
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
PWAM signalling scheme for high speed serial link transceiver design
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
Low-power, high-speed transceivers for network-on-chip communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, capacitive 4-PWAM transmitter architectures and circuits are proposed and its performances are analyzed with random jitter and PVT variation comparing with other works. A novel technique is proposed to reduce power and to increase speed by using capacitive driven low swing transceiver. The proposed design saves 1.74~2.4x power and 4x higher data rate than conventional designs. To implement 4-PWAM transmitter new phase controller and adaptive capacitance network are designed. At receiver side, new architectures for PWM and PAM demodulation are proposed.