A global router based on a multicommodity flow model
Integration, the VLSI Journal
Optimal wire sizing and buffer insertion for low power and a generalized delay model
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Rectangle-packing-based module placement
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Delay bounded buffered tree construction for timing driven floorplanning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Closed form solution to simultaneous buffer insertion/sizing and wire sizing
Proceedings of the 1997 international symposium on Physical design
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Performance driven multi-layer general area routing for PCB/MCM designs
DAC '98 Proceedings of the 35th annual Design Automation Conference
Partitioning by iterative deletion
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Integrated floorplanning and interconnect planning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
An iterative-improvement penalty-function-driven wire routing system
IBM Journal of Research and Development
Planning buffer locations by network flows
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Repeater block planning under simultaneous delay and transition time constraints
Proceedings of the conference on Design, automation and test in Europe
Integrated power supply planning and floorplanning
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Routability driven floorplanner with buffer block planning
Proceedings of the 2002 international symposium on Physical design
Buffer block planning for interconnect planning and prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
An algorithm for integrated pin assignment and buffer planning
Proceedings of the 39th annual Design Automation Conference
An integrated floorplanning with an efficient buffer planning algorithm
Proceedings of the 2003 international symposium on Physical design
Dynamic global buffer planning optimization based on detail block locating and congestion analysis
Proceedings of the 40th annual Design Automation Conference
Multilevel floorplanning/placement for large-scale modules using B*-trees
Proceedings of the 40th annual Design Automation Conference
A buffer planning algorithm with congestion optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Buffer allocation algorithm with consideration of routing congestion
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Integrating buffer planning with floorplanning for simultaneous multi-objective optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Accurate and efficient flow based congestion estimation in floorplanning
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Interconnect Planning with Local Area Constrained Retiming
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Buffer Planning Algorithm Based on Partial Clustered Floorplanning
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An algorithm for integrated pin assignment and buffer planning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simultaneous floorplanning and buffer block planning
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A buffer planning algorithm based on dead space redistribution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Improved timing closure by early buffer planning in floor-placement design flow
Proceedings of the 17th ACM Great Lakes symposium on VLSI
An effective buffer planning algorithm for IP based fixed-outline SOC placement
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Handling routability in floorplan design with twin binary trees
Integration, the VLSI Journal
POMR: a power-aware interconnect optimization methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Buffer planning for IP placement using sliced-LFF
VLSI Design - Special issue on CAD for Gigascale SoC Design and Verification Solutions
A new buffer planning algorithm based on room resizing
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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