Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Planning buffer locations by network flows
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Routability-driven repeater block planning for interconnect-centric floorplanning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An integrated floorplanning with an efficient buffer planning algorithm
Proceedings of the 2003 international symposium on Physical design
Dynamic global buffer planning optimization based on detail block locating and congestion analysis
Proceedings of the 40th annual Design Automation Conference
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The dominating contribution of interconnect to system performance has made it critical to plan the buffers and the routes resource in the early stage of the layout. In this paper, we present a congestion estimation model which takes the buffer insertion sites into consideration. Based on the feasible region of the buffer insertion, the two-level tile structure is used to represent the distribution of the feasible buffer insertion sites among the routing tiles. And the buffer allocation method is performed based on the congestion estimation, which can find the buffer locations with good congestion result. Our approach can be embedded into the floorplanning process and the experimental results show the efficiency of our method.