Planning buffer locations by network flows
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Routability-driven repeater block planning for interconnect-centric floorplanning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
VLSI block placement using less flexibility first principles
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Routability driven floorplanner with buffer block planning
Proceedings of the 2002 international symposium on Physical design
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs
Proceedings of the 2002 international symposium on Physical design
Provably good global buffering using an available buffer block plan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Simultaneous floorplanning and buffer block planning
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A buffer planning algorithm based on dead space redistribution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Interconnect performance estimation models for design planning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Buffer planning as an Integral part of floorplanning with consideration of routing congestion
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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More and more IP cores are used in modern SOC designing. In order to place IP cores effectively, hierarchical design has been introduced and better supported by fixed-outline floorplanning than outline-free [1]. In this paper, we also consider buffer insertion issue in fixed-outline floorplanning with the help of the Less Flexibility First (LFF) algorithm, which runs in a fixed-outline area and places IP cores as hard modules one after another with no backtracks. Unlike Simulated Annealing (SA), LFF is a deterministic packing algorithm and runs without topological representations. Therefore, it is able to tell the difference among geometric floorplans with the same topological structure, which is helpful to get a better result for buffer planning since buffer insertions are quite sensitive to a geometric change. Moreover, a 2-staged packing and a post greedy method after packing are also introduced based on a net-classing strategy and finally help to achieve great success rate improvement of buffer insertion (about +40.7% in 0.18um and +37.1% in 0.07μm). Meanwhile, our buffer planning method runs much faster than SA, since it is deterministic and has no backtracks. Besides, it is also useful to provide an initial solution for SA for further optimization.