Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Planning buffer locations by network flows
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Routability-driven repeater block planning for interconnect-centric floorplanning
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Buffer block planning for interconnect-driven floorplanning
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Provably good global buffering by multi-terminal multicommodity flow approximation
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A practical methodology for early buffer and wire resource allocation
Proceedings of the 38th annual Design Automation Conference
Routability driven floorplanner with buffer block planning
Proceedings of the 2002 international symposium on Physical design
Integrated floorplanning with buffer/channel insertion for bus-based microprocessor designs
Proceedings of the 2002 international symposium on Physical design
Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Provably good global buffering using an available buffer block plan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Dynamic global buffer planning optimization based on detail block locating and congestion analysis
Proceedings of the 40th annual Design Automation Conference
Fast buffer planning and congestion optimization in interconnect-driven floorplanning
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
A buffer planning algorithm based on dead space redistribution
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Estimating routing congestion using probabilistic analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Floorplanning with Consideration of White Space Resource Distribution for Repeater Planning
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
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This paper studies the problem of buffer planning for interconnect-centric floorplanning. We devise a congestion-driven buffer insertion algorithm, in which single-pair shortest-path model is used to compute optimal buffer locations and simultaneously to preserve the monotonicity of routing paths. Congestion estimation is achieved by an approach of probabilistic analysis. In order to get more buffers inserted, on the basis of a rough estimation of buffer locations, some channels determined by the boundaries of circuit block are inserted, while the topology of the placement keeps unchanged. Furthermore, we change the distribution of the dead space among blocks to optimize the time closure and routing congestion. The performance of the chip can be improved greatly on penalty of a small area usage. The effectiveness of the proposed algorithm has been demonstrated by the experimental results.