Wire segmenting for improved buffer insertion
DAC '97 Proceedings of the 34th annual Design Automation Conference
Planning buffer locations by network flows
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Buffer block planning for interconnect planning and prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
An integrated floorplanning with an efficient buffer planning algorithm
Proceedings of the 2003 international symposium on Physical design
Dynamic global buffer planning optimization based on detail block locating and congestion analysis
Proceedings of the 40th annual Design Automation Conference
A buffer planning algorithm with congestion optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Routability-driven repeater block planning for interconnect-centric floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Provably good global buffering by generalized multiterminal multicommodity flow approximation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Routability-driven floorplanner with buffer block planning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integrated floorplanning with buffer/channel insertion for bus-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimization of the bias current network for accurate on-chip thermal monitoring
Proceedings of the Conference on Design, Automation and Test in Europe
Optimization of the bias current network for accurate on-chip thermal monitoring
Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper, we proposed an effective and efficient model to evaluate the white space resource distribution in the floorplan/placement. The model discretizes the chip with a homogeneous rectangular mesh, in which the cost of each grid depends on the white space area and the routing congestion. The model has gotten application in our floorplanner to plan a good white space resources distribution to favor the later stage of repeater planning. On the other hand, non-zero area white-space blocks, which will join the formation of floorplan configurations, are introduced to adjust the amount and distribution of white space resources. Finally, a novel graph-based repeater assignment algorithm is devised to achieve the repeater planning. The number of nets failed to meet the repeater insertion constraint is reduced by 15.6% on penalty of 2.2% area usage reduction.