Minimum padding to satisfy short path constraints
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Energy-efficient signal processing via algorithmic noise-tolerance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Closed-loop adaptive voltage scaling controller for standard-cell ASICs
Proceedings of the 2002 international symposium on Low power electronics and design
Statistical timing analysis using bounds and selective enumeration
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Death, taxes and failing chips
Proceedings of the 40th annual Design Automation Conference
Statistical timing for parametric yield prediction of digital integrated circuits
Proceedings of the 40th annual Design Automation Conference
Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Designing robust microarchitectures
Proceedings of the 41st annual Design Automation Conference
Modeling, testing, and analysis for delay defects and noise effects in deep submicron devices
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical timing analysis using bounds and selective enumeration
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Method for formal verification of soft-error tolerance mechanisms in pipelined microprocessors
ICFEM'10 Proceedings of the 12th international conference on Formal engineering methods and software engineering
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Delay variation can cause a design to fail its timing specification. Ernst et al. [2003] observe that the worst delay of a design is least probable to occur. They propose a mechanism to detect and correct occasional errors while the design can be optimized for the common cases. Their experimental results show significant performance (or power) gain as compared with the worst-case design. However, the architecture in Ernst et al. [2003] suffers the short path problem, which is difficult to resolve. In this article, we propose a novel error-detecting architecture to solve the short path problem. Our experimental results show considerable performance gain can be achieved with reasonable area overhead.