Protecting digital circuits against hold time violation due to process variability

  • Authors:

  • Gustavo Neuberger;Gilson Wirth;Ricardo Reis

  • Affiliations:

  • Universidade Federal do Rio Grande do Sul (UFRGS), Porto Aleqre -- RS- Brazil;Universidade Federal do Rio Grande do Sul (UFRGS), Porto Aleqre -- RS- Brazil;Universidade Federal do Rio Grande do Sul (UFRGS), Porto Aleqre -- RS- Brazil

  • Venue:
  • Proceedings of the 22nd Annual Symposium on Integrated Circuits and System Design: Chip on the Dunes
  • Year:
  • 2009

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Abstract

Statistical process variations are a critical issue to define circuit design strategies to ensure high yield in sub-100nm technologies. This work focuses on hold time violation probabilities in sub-100 nm technologies. The variability in flip-flop race immunity and clock skew is evaluated, and a methodology for the estimation of hold time violation probability is developed. This violation probability is analyzed at different technologies, flip-flop strength, supply voltage and padding. Then three different methods to protect against hold time violations are evaluated: Vdd reduction, race immunity increase, and padding. Each of them has different advantages and drawbacks that must be taken into account. It is shown that at design time the most effective method is padding. An algorithm to automatically insert padding in digital circuits considering process variability is presented. The proposed algorithm will be evaluated compared to other ways to protect against violations.