Clock skew scheduling with race conditions considered
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock period minimization with minimum delay insertion
Proceedings of the 44th annual Design Automation Conference
Leakage power-aware clock skew scheduling: converting stolen time into leakage power reduction
Proceedings of the 45th annual Design Automation Conference
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It is well known that the clock skew can be exploited as a manageable resource to improve circuit performance. However, due to the limitation of race conditions, the optimal clock skew scheduling often does not achieve the lower bound of sequential timing optimization. This paper proposes a polynomial time complexity algorithm, called delay insertion and nonzero skew algorithm (DIANA), which considers delay insertion to determine the clock skew schedule. The objective here is not only to optimize the clock period but also to heuristically minimize the required inserted delay for resolving the race conditions. Experiments with benchmark circuits consistently demonstrate that the proposed approach achieves the lower bound of sequential timing optimization. Moreover, since the DIANA algorithm attempts to minimize the required inserted delay between two registers, the feasible value for delay insertion is within a very large range. Therefore, even though only the buffers in a standard cell library are used to implement the delay insertion, a feasible solution is easily found