A realizable driving point model for on-chip interconnect with inductance
Proceedings of the 37th Annual Design Automation Conference
Current-mode signaling in deep submicrometer global interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Modeling of on-chip bus switching current and its impact on noise in power supply grid
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Energy consumption in RC tree circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Differential current-sensing for on-chip interconnects
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and modeling of energy consumption in RLC tree circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis and future trend of short-circuit power
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modeling the “Effective capacitance” for the RC interconnect of CMOS gates
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, energy dissipation in resistance-inductance-capacitance (RLC) current-mode signaling is modeled. The energy dissipation is derived separately for driver, wire, and receiver termination. The effects of rise time and clock cycle are included. A realizable Π-model for the driving-point impedance of an RLC current-mode transmission line is derived. The output current of an RLC current-mode transmission line is also derived. The model is extended to multiple parallel coupled interconnects with inductive and capacitive coupling between them. The model is verified by comparing it to HSPICE in 65-nm technology and applied to differential current-mode signaling.