Simplified delay design guidelines for on-chip global interconnects

Authors:
Liang Zhang;Wentai Liu;Rizwan Bashirullah;John Wilson;Paul Franzon
Affiliations:
North Carolina State University, Raleigh, NC;University of California at Santa Cruz, Santa Cruz, CA;North Carolina State University, Raleigh, NC;North Carolina State University, Raleigh, NC;North Carolina State University, Raleigh, NC
Venue:
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Year:
2004

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Abstract

Based on the effective attenuation constant approximation of distributed RLC lines, simplified design guidelines are presented dealing with the line characteristics, termination, and delay estimation of on-chip global interconnects. RC delay models are verified to be still accurate for a wide range of parameters conventionally considered inductive. A new closed-form RLC delay formula is developed when RC models are inadequate. The formula works for both voltage and current-mode signaling and exhibits 10% accuracy of SPICE simulation. This work is suitable for global routing topologies and iterative layout optimization.