CMOS sensors for on-line thermal monitoring of VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
System-level performance evaluation of three-dimensional integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Proceedings of the 39th annual Design Automation Conference
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Thermal via planning for 3-D ICs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Analytical Model for the Propagation Delay of Through Silicon Vias
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
Energy-efficient variable-flow liquid cooling in 3D stacked architectures
Proceedings of the Conference on Design, Automation and Test in Europe
On signalling over through-silicon via (TSV) interconnects in 3-D integrated circuits
Proceedings of the Conference on Design, Automation and Test in Europe
Dynamic thermal management in 3D multicore architectures
Proceedings of the Conference on Design, Automation and Test in Europe
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Thermal sensing is a pressing need in stacked 3-D chips with limited number of vertical heat conduits. In 3-D systems with active temperature control, the controller is reliant on sensors placed on individual planes to provide the necessary thermal feedback. To this end we propose a delay-line based thermal-sensor which provides a high temperature-sensitivity, high level of process-robustness and is amenable to the TSV-based communication paradigm used in 3D systems. The temperature-sensitive piece mitigates the high process-susceptibility of 3-D circuits through usage of multiple logic-stages composed of long-channel devices and elimination of common-mode noise on the delay-line pair. The thermal information is conveyed to the controller in the form of a signal-frequency and hence is insensitive to path-mismatch in TSV wires. A high post-digitization temperature sensitivity of 0.82%/°C was achieved. The 1-σ accuracy loss due to process-variations and supply-noise was limited to 0.78°C and 1.06°C respectively indicating a high level of process-tolerance.