Randomized rounding: a technique for provably good algorithms and algorithmic proofs
Combinatorica - Theory of Computing
A fast and low cost testing technique for core-based system-on-chip
DAC '98 Proceedings of the 35th annual Design Automation Conference
Design of system-on-a-chip test access architectures under place-and-route and power constraints
Proceedings of the 37th Annual Design Automation Conference
Optimal test access architectures for system-on-a-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Introduction to Linear Optimization
Introduction to Linear Optimization
Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
Using Partial Isolation Rings to Test Core-Based Designs
IEEE Design & Test
A structured test re-use methodology for core-based system chips
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A structured and scalable mechanism for test access to embedded reusable cores
ITC '98 Proceedings of the 1998 IEEE International Test Conference
SOC Test Scheduling Using Simulated Annealing
VTS '03 Proceedings of the 21st IEEE VLSI Test Symposium
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Effective and Efficient Test Architecture Design for SOCs
ITC '02 Proceedings of the 2002 IEEE International Test Conference
Cluster-Based Test Architecture Design for System-on-Chip
VTS '02 Proceedings of the 20th IEEE VLSI Test Symposium
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Global interconnect design in a three-dimensional system-on-a-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3D Processing Technology and Its Impact on iA32 Microprocessors
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
Multi-Frequency Test Access Mechanism Design for Modular SOC Testing
ATS '04 Proceedings of the 13th Asian Test Symposium
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Interconnect and Thermal-aware Floorplanning for 3D Microprocessors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Interactive presentation: An SoC test scheduling algorithm using reconfigurable union wrappers
Proceedings of the conference on Design, automation and test in Europe
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
IEEE Transactions on Computers
Scan-chain design and optimization for three-dimensional integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Test Challenges for 3D Integrated Circuits
IEEE Design & Test
On-Chip TSV Testing for 3D IC before Bonding Using Sense Amplification
ATS '09 Proceedings of the 2009 Asian Test Symposium
Proceedings of the 2009 International Conference on Computer-Aided Design
Test architecture design and optimization for three-dimensional SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient test solutions for core-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test planning for modular testing of hierarchical SOCs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
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Embedded cores in a core-based system-on-chip (SOC) are not easily accessible via chip I/O pins. Test-access mechanisms (TAMs) and test wrappers (e.g., the IEEE Standard 1500 wrapper) have been proposed for the testing of embedded cores in a core-based SOC in a modular fashion. We show that such a modular testing approach can also be used for emerging three-dimensional integrated circuits based on through-silicon vias (TSVs). Core-based SOCs based on 3D IC technology are being advocated as a means to continue technology scaling and overcome interconnect-related bottlenecks. We present an optimization technique for minimizing the post-bond test time for 3D core-based SOCs under constraints on the number of TSVs, the TAM bitwidth, and thermal limits. The proposed optimization method is based on a combination of integer linear programming, LP-relaxation, and randomized rounding. It considers the Test Bus and TestRail architectures, and incorporates wire-length constraints in test-access optimization. Simulation results are presented for the ITC 02 SOC Test Benchmarks and the test times are compared to that obtained when methods developed earlier for two-dimensional ICs are applied to 3D ICs. The test time dependence on various 3D parameters (e.g. 3D placement, the number of layers, thermal constraints, and the number of TSVs) is also studied.