Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip
Journal of Electronic Testing: Theory and Applications
Wrapper Design for Embedded Core Test
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Optimal Core Wrapper Width Selection and SOC Test Scheduling Based on 3-D Bin Packing Algorithm
ITC '02 Proceedings of the 2002 IEEE International Test Conference
SOC test architecture design for efficient utilization of test bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
Design space exploration for 3D architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Scan-chain design and optimization for three-dimensional integrated circuits
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Test-access mechanism optimization for core-based three-dimensional SOCs
Microelectronics Journal
Test architecture design and optimization for three-dimensional SoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Efficient test solutions for core-based designs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Optimization Methods for Post-Bond Testing of 3D Stacked ICs
Journal of Electronic Testing: Theory and Applications
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System-on-chip (SOC) designs comprised of a number of embedded cores are widespread in today's integrated circuits. Embedded core-based design is likely to be equally popular for three-dimensional integrated circuits (3D ICs), the manufacture of which has become feasible in recent years. 3D integration offers a number of advantages over traditional two-dimensional (2D) technologies, such as the reduction in the average interconnect length, higher performance, lower interconnect power consumption, and smaller IC footprint. Despite recent advances in 3D fabrication and design methods, no attempt has been made thus far to design a 1500-style test wrapper for an embedded core that spans multiple layers in a 3D SOC. This paper addresses wrapper optimization in 3D ICs based on through-silicon vias (TSVs) for vertical interconnects. Our objective is to minimize the scan-test time for a core under constraints on the total number of TSVs available for testing. We present two polynomial-time heuristic solutions. Simulation results are presented for embedded cores from the ITC 2002 SOC test benchmarks.