Extending systems-on-chip to the third dimension: performance, cost and technological tradeoffs
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Timing-driven via placement heuristics for three-dimensional ICs
Integration, the VLSI Journal
Automated module assignment in stacked-Vdd designs for high-efficiency power delivery
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Thermomechanical modeling of 3D electronic packages
IBM Journal of Research and Development
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance and thermal-aware Steiner routing for 3-D stacked ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SOC'09 Proceedings of the 11th international conference on System-on-chip
Cost-aware three-dimensional (3D) many-core multiprocessor design
Proceedings of the 47th Design Automation Conference
Invited paper: Thermal modeling and analysis of 3D multi-processor chips
Integration, the VLSI Journal
Low-Power Hypercube Divided Memory FFT Engine Using 3D Integration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fabrication cost analysis and cost-aware design space exploration for 3-D ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Emulation-based transient thermal modeling of 2D/3D systems-on-chip with active cooling
Microelectronics Journal
Power delivery design for 3-D ICs using different through-silicon via (TSV) technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A linear-time approach for the transient thermal simulation of liquid-cooled 3d ics
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Distributed TSV topology for 3-D power-supply networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
TSV redundancy: architecture and design issues in 3-D IC
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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As thermal problems become more evident, new physical design paradigms and tools are needed to alleviate them. Incorporating thermal vias into integrated circuits (ICs) is a promising way of mitigating thermal issues by lowering the effective-thermal resistance of the chip. However, thermal vias take up valuable routing space, and therefore, algorithms are needed to minimize their usage while placing them in areas where they would make the greatest impact. With the developing technology of three-dimensional integrated circuits (3-D ICs), thermal problems are expected to be more prominent, and thermal vias can have a larger impact on them than in traditional two-dimensional integrated circuits (2-D ICs). In this paper, thermal vias are assigned to specific areas of a 3-D IC and used to adjust their effective-thermal conductivities. The method, which uses finite-element analysis (FEA) to calculate temperatures quickly during each iteration, makes iterative adjustments to these thermal conductivities in order to achieve a desired thermal objective and is general enough to handle a number of different thermal objectives such as achieving a desired maximum operating temperature. With this method, 49% fewer thermal vias are needed to obtain a 47% reduction in the maximum temperatures, and 57% fewer thermal vias are needed to obtain a 68% reduction in the maximum thermal gradients than would be needed using a uniform distribution of thermal vias to obtain these same thermal improvements. Similar results were seen for other thermal objectives, and the method efficiently achieves its thermal objective while minimizing the thermal-via utilization.