High aspect ratio via metallization for 3D integration using CVD TiN barrier and electrografted Cu seed

  • Authors:

  • G. Druais;G. Dilliway;P. Fischer;E. Guidotti;O. Lühn;A. Radisic;S. Zahraoui

  • Affiliations:

  • STMicroelectronics assigned at IMEC, Kapeldreef 75, B-3001 Leuven, Belgium;ASM Belgium NV, Kapeldreef 75, B-3001 Leuven, Belgium;ASM Belgium NV, Kapeldreef 75, B-3001 Leuven, Belgium;Alchimer, 15, rue du Buisson aux Fraises, F-91300 Massy, France;IMEC, Kapeldreef 75, B-3001 Leuven, Belgium;IMEC, Kapeldreef 75, B-3001 Leuven, Belgium;Alchimer, 15, rue du Buisson aux Fraises, F-91300 Massy, France

  • Venue:
  • Microelectronic Engineering
  • Year:
  • 2008

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Abstract

3D integration is of high interest to overcome the future challenges that are to be met both by device interconnections and packaging. In between the challenges that are to be met to achieve this process is the via fill when making high aspect ratio vias and barrier and seed deposition layers deposition. In this paper, we showed that we were able to achieve a good continuity with a good conformality for barrier and seed layers in Aspect Ratio 10 vias, using respectively CVD TiN and eG ViaCoat^(TM) Cu seed. The studied vias are 5@mm wide and 50@mm deep. We first demonstrated the continuity of the barrier by performing a HF-dip test on trenches structures and, after having run a DOE to optimize seed layer deposition recipe, we did some early test of via fill to assess the continuity of the barrier/seed stack.