Demystifying 3D ICs: The Pros and Cons of Going Vertical
IEEE Design & Test
A reconfigurable architecture for hybrid CMOS/Nanodevice circuits
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
3D chip-stacking technology with through-silicon vias and low-volume lead-free interconnections
IBM Journal of Research and Development
Monolithically stackable hybrid FPGA
Proceedings of the Conference on Design, Automation and Test in Europe
Array-based architecture for FET-based, nanoscale electronics
IEEE Transactions on Nanotechnology
Reconfigurable Hybrid CMOS/Nanodevice Circuits for Image Processing
IEEE Transactions on Nanotechnology
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In this paper, we give an overview of our recent research efforts on monolithic 3D integration of CMOS and memristive nanodevices. These hybrid circuits combine a CMOS subsystem with several layers of nanowire crossbars, consisting of arrays of two-terminal memristors, all connected by an area-distributed interface between the CMOS subsystem and the crossbars. This approach combines the advantages of CMOS technology, including its high flexibility, functionality and yield, with the extremely high density of nanowires, nanodevices and interface vias. As a result, the 3D hybrids can overcome limitations pertinent to other 3D integration techniques (such as through-silicon vias) and enable 3D circuits with unprecedented memory density (up to 1014 bits on a single 1-cm2 chip) and aggregate interlayer communication bandwidth (up to 1018 bits per second per cm2) at manageable power dissipation. Such performance represents a significant step towards addressing the most pressing needs of modern compact electronic systems.